Stalls in an instruction pipeline due to cache misses or other memory transactions can reduce the efficiency of a processor. This problem is exacerbated in multithreaded processors, as a stall in the instruction pipeline due to one thread can delay execution of other threads. Some processors monitor the instruction pipeline for stalls independent of a program flow, and in response to a stall grant a thread other than the one causing the stall priority to be executed in the pipeline. However, monitoring for a stall in an instruction pipeline is typically difficult and requires additional overhead at the processor. Accordingly, there is a need for an improved technique for allocating processor resources to threads in a multithreaded processor.